Minutes, IBIS Quality Committee

20 feb 2007

11-12 AM EST (8-9 AM PST)

ROLL CALL
  Adam Tambone
  Barry Katz
  Benny Lazer
  Benjamin P Silva
* Bob Ross, Teraspeed Consulting Group
  Brian Arsenault
* David Banas, Xilinx
* Eckhard Lenski
  Eric Brock
  Gregory R Edlund
  Hazem Hegazy
  John Figueroa
  John Angulo
  Katja Koller
  Kevin Fisher
* Kim Helliwell, LSI Logic
  Lance Wang
  Lynne Green
* Mike LaBonte, Cisco
* Moshiul Haque, Micron Technology
  Peter LaFlamme
  Radovan Vuletic, Qimonda
  Robert Haller
* Roy Leventhal, Leventhal Design & Communications
  Sherif Hammad
  Todd Westerhoff
  Tom Dagostino
  Kazuyoshi Shoji
  Sadahiro Nonoyama

Everyone in attendance marked by  *

NOTE: "AR" = Action Required.

-----------------------MINUTES ---------------------------
Mike LaBonte conducted the meeting.

AR Review:

- Mike add IBISCHK info back into IQ spec & checklist
  Done. Some message examples are TBD. Proposals not inserted.
  Checklist not updated.

- Kim remove 4.1.3 and add to 4.1.4, send to Mike
  Done.

- Bob check on draft 1.1h doc versions
  Done. The file sent by Moshiul is correct.

- All review IQ 2.1 and comment by email
  Roy read it; no comments.

New items:

Renumbering of checks in IQ specification
- The 4.1.3 check is deleted, do we renumber the subsequent checks
  or leave a gap?
- Might affect released files that use current numbering
- Moshiul has no problem with changing numbers of existing checks.
- We will renumber when we produce the release document.

New 4.1.4
- Needs to be level 2
- Comments about IBIS 4.0 C_comp:
  - Should give subparams literally.
  - Should be split off as a level 4 check
    - The 4 C_comp_xxx parameters are there to get supply currents right.
- We are essentially done with 4.1.4, with just a few changes.

AR: Mike change 4.1.4 to level 2
AR: David write 4.1.4a require 4.0 C_comp subparams to achieve level 4

David looked at Roy's slides and gave input. Need to pick and choose
to cut down the length.

Will we drive IBIS to achieve 10ps accuracy?
- Roy: This may be achievable in simulation, but not in measurement
- Xilinx has a "5 features" criteria
  - The 10% time error criteria = 50ps for DDR3
  - Roy: if 10% is pass/fail criteria, the designer is not in the right
    "design space"
  - Mike uses 5% for a similar metric for evaluating package skew

AR: Roy will send new version of his presentation to individuals for comment

When will IQ 1.1 be ratified?
- It's not that formal, no ANSI/EIA registration
- We move IQ specs to the top web page link when they are ready

Next meeting:

27 Feb 2007
11-12 AM EST (8-9 AM PST)
We will use Meetme again
Phone: 1.877.384.0543 or 1.800.743.7560
Passcode: 90437837

Meeting ended at 12:08 PM Eastern Time.